Textbook in PDF format

Introduction and basics
What is asynchronous advantages and disadvantages design styles
hazards and races control/data dichotomy
Specification and synthesis methodologies
Event based models concurrent languages FSMs
Synthesis from Signal Transition Graphs
Synthesis fow state assignment logic synthesis design for testability
comparison with synchronous
Verification and validation of asynchronous designs
Formal verification checking properties validation in VHDL environment
Practical applications
Interface design asynchronous processors DSP circuits CAD t